High speed image sensors have been widely used in many applications in different fields including the automotive field, the machine vision field, and the field of professional video photography. The development of high speed image sensors is further driven by the consumer market's continued demand for high speed slow motion video and normal high-definition (HD) video that have a reduced rolling shutter effect.
In conventional complementary metal-oxide semiconductor (“CMOS”) pixel cell, image charge is transferred from a photosensitive device (e.g., a photodiode) and is converted to a voltage signal inside the pixel cell on a floating diffusion node. The image charge can be readout from the pixel cell into readout circuitry and then processed. In conventional CMOS image sensors, the readout circuit includes an analog-to-digital converter (ADC). One type of ADC is the successive approximation ADC which converts the analog signal using a binary search. This binary search is implemented using a successive approximation register (SAR) that counts by trying all values of bits starting with the most-significant bit (MSB) and finishing at the least-significant bit (LSB) to converge upon a digital output that is the conversion of the analog signal.
However, in image sensors with SAR ADC, several percentages of the ADC range may be lost due to the need for an analog data pedestal to avoid clipping of offset and noise. For example, if the pedestal is 60 LSB or 160 LSB, the maximum range for a 12-bit ADC is 4036 LSB (e.g., 4096 LSB-60 LSB) or 3936 LSB (e.g., 4096 LSB-160 LSB). Thus, the analog pedestal reduces the maximum ADC range. While digital gain may be applied to stretch the maximum output to the desired range of 4096 LSB, the ADC is not a true 12-bit ADC.
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